The invention realtes to a clock signal arrangement comprising a first clock signal regenerator connected to an input terminal and including a first phase control loop, the phase control loop comprising a first voltage-controlled oscillator for producing a first oscillator signal and first divider connected thereto for supplying a first regenerated clock signal.
Such a clock signal regenerator is described in an article entitled "Phasenregelkreis (PLL)" published in Funkschau no. 6, pages 61-68, 1983. FIG. 2 of the article shows a phase control loop in which a signal from a voltage-controlled oscillator is applied to a phase detector via a divider and a phase difference is determined, using an input signal. In the phase detector a phase difference signal is determined which via a control voltage circuit is applied to an oscillator with the aid of which the voltagecontrolled oscillator is detuned such that the phase difference is reduced.
Such a clock signal regenerator does not, however, ensure that a reliable output clock signal having an adequate phase accuracy is generated; this holds more specifically for the case in which, for example, no control voltage is applied to the voltagecontrolled oscillator because of a defect; the oscillator is then namely in the "free running" state.